1. Field
Various exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a controller, a semiconductor memory system, a data storage system and an operating method thereof.
2. Description of the Related Art
In general, semiconductor memory devices are classified into volatile memory devices, representatively such as Dynamic Random Access Memory (DRAM) and Static RAM (SRAM), and non-volatile memory devices, representatively such as Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable PROM (EPROM), Electrically EPROM (EEPROM), Ferromagnetic RAM (FRAM), Phase change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM) and flash memory.
The volatile memory device loses data stored therein when power supply thereto is interrupted, whereas a non-volatile memory device retains data stored therein even when power supply thereto is interrupted. The flash memory device as the non-volatile memory device is widely used as a storage medium in a computer system because of its high program speed, low power consumption and large data storage capacity.
In the non-volatile memory device, especially in the flash memory device, states of data of each memory cell depend on the number of bits that the memory cell can program. A memory cell storing 1-bit data per cell is called a single-bit cell or a single-level cell (SLC). A memory cell storing multi-bit data (i.e., 2 or more bits data) per cell is called a multi-bit cell, a multi-level cell (MLC) or a multi-state cell. The MLC is advantageous for high integration. However, as the number of bits programmed in each memory cell increase, the reliability decreases and the read failure rate increases.
For example, when k bits are to be programmed in a memory cell, one of 2k threshold voltages is formed in the memory cell. Due to the minute differences between the electrical characteristics of memory cells, the threshold voltages of memory cells programmed for the same data form threshold voltage distribution. The threshold voltage distributions correspond to 2k data values representing k-bit information, respectively.
However, a voltage window available for the threshold voltage distributions is finite. Therefore, as the value k increases, the distance between the threshold voltage distributions decreases and the neighboring threshold voltage distributions overlap each other. As the neighboring threshold voltage distributions overlap each other, read data may include several or several tens of error bits.
FIG. 1 is a threshold voltage distribution schematically illustrating program and erase states of a 3-bit multi-level cell (3-bit MLC) non-volatile memory device.
FIG. 2 is a threshold voltage distribution schematically illustrating program and erase states due to characteristic deterioration of the 3-bit MLC non-volatile memory device.
In the MLC non-volatile memory device, e.g., the MLC flash memory device capable of storing k-bit data in a single memory cell, the memory cell may have one of 2k threshold voltage distributions. For example, the 3-bit MLC has one of 8 threshold voltage distributions.
The threshold voltages of memory cells programmed for the same data form the threshold voltage distribution due to characteristic differences between memory cells. In the 3-bit MLC non-volatile memory device, as illustrated in FIG. 1, the threshold voltage distributions are formed in correspondence with the data states including 7 program states ‘P1’ to ‘P7’ and an erase state ‘E’.
FIG. 1 shows an ideal case in which the threshold voltage distributions do not overlap and have read voltage margins therebetween. Referring to the flash memory example of FIG. 2, the memory cell may experience charge loss that electrons trapped at a floating gate or tunnel oxide film are discharged over time. Such charge loss may accelerate when the tunnel oxide film deteriorates by iterative program and erase operations. The charge loss results in a decrease in the threshold voltages of memory cells. For example, as illustrated in FIG. 2, the threshold voltage distribution may be shifted left due to charge loss.
Further, program disturbance, erase disturbance and/or back pattern dependency also cause increases in threshold voltages. As characteristics of memory cells deteriorate, neighbouring threshold voltage distributions may overlap, as illustrated in FIG. 2.
Once neighbouring threshold voltage distributions overlap, read data may include a significant number of errors when a particular read voltage is applied to a selected word line. For example, when a sensed state of a memory cell according to a read voltage Vread3 applied to a selected word line is on, the memory cell is determined to have a second program state ‘P2’. When a sensed state of a memory cell according to a read voltage Vread3 applied to a selected word line is off, the memory cell is determined to have a third program state ‘P3’. However, when neighbouring threshold voltage distributions overlap, the memory cell actually having the third program state ‘P3’ may be erroneously determined to have the second program state ‘P2’. In short, when the neighbouring threshold voltage distributions overlap as illustrated in FIG. 2, read data may include a significant number of errors.
What is therefore required is a scheme for precisely reading data stored in memory cells of a semiconductor memory device.